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1. general description the tea5766uk is a single chip electronically tuned fm stereo radio with radio data system (rds) and radio broadcast data system (rbds) demodulator and rds/rbds decoder, for portable application with fully integrated intermediate frequency (if) selectivity and fm demodulation. the radio is completely adjustment free and only requires a minimum of small and low cost external components. the radio can tune to the european, us and japanese fm bands. it has a low power consumption at a low supply voltage. the tea5766uk application software is compatible to the tea5764 software to enable easy design-in for customers. 2. features n high sensitivity due to integrated low noise radio frequency (rf) input ampli?er n fm mixer for conversion of the us/europe (87.5 mhz to 108 mhz) and japanese fm band (76 mhz to 90 mhz) to if n preset tuning to receive japanese tv audio up to 108 mhz n autonomous search tuning, 100 khz grid n rf automatic gain control circuit n lc tuner oscillator operating with integrated varicaps and one low-cost chip inductor n fully integrated fm if selectivity n fully integrated fm demodulator n 32768 hz external reference frequency n phase locked loop (pll) synthesizer tuning system n if counter, 7-bit output via control interface n level detector, 4-bit level information output via the control interface n soft mute, signal depending mute function, can be switched on or off via the control interface n mono/stereo blend, signal depending gradual change from mono to stereo, can be switched on or off via the control interface n standby mode n software programmable port n fully integrated rds/rbds demodulator in accordance with en 62106 n rds/rbds decoder with memory for two rds data blocks provides block synchronization and error correction; block data and status information are available via the i 2 c-bus tea5766uk stereo fm radio + rds rev. 01 22 march 2007 product data sheet
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 2 of 59 nxp semiconductors tea5766uk stereo fm radio + rds n interrupt ?ag n interrupt line 3. quick reference data [1] includes both analog supply current on pin v cca and vco supply current on pin v cc(vco) . 4. ordering information table 1. quick reference data under all conditions a reference clock of 32.768 khz is present. symbol parameter conditions min typ max unit general electrical parameters v cca analog supply voltage 2.6 2.7 3.6 v v cc(vco) vco supply voltage 2.6 2.7 3.6 v i cca analog supply current operating [1] - 13.5 17 ma standby mode [1] --5 m a v ccd digital supply voltage 2.6 2.7 3.6 v i ccd digital supply current operating; rds off - 350 450 m a operating; rds on - 0.75 1.5 ma standby mode - 5 10 m a sleep mode; only in i 2 c-bus; busen = high -1625 m a v vrefdig voltage on pin vrefdig v vrefdig v ccd 1.65 1.8 v ccd v i vrefdig current on pin vrefdig 0 0.5 1 m a standby mode 0 0.5 1 m a general operating conditions f i(fm) fm input frequency 76 - 108 mhz t amb ambient temperature device meets all speci?cations - 20 - +85 c tea5766uk functional, speci?cation not guaranteed - 30 - +85 c table 2. ordering information type number package name description version tea5766uk wlcsp25 wafer level chip-size package; 25 bumps; 3.3 3.25 0.6 mm tea5766
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 3 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 5. block diagram fig 1. block diagram 001aaf442 2 if filter n1 i/q mixer 1st fm rf agc power supply auto align reference buffer soft mute sds i 2 c-bus interface mpx decoder tuning system mono pilot prog. div out ref. div out mux sw port vco gndd d6 e6 e5 e4 tmute vafr vafl mpxout iss busen intx limiter level adc demodulator 57 khz bp filter rds/rbds decoder interface register if counter tea5766uk gnda b5 c1 b6 c6 c5 freqin a6 v cca rfin1 rfin2 gnd(rf) a2 a1 a3 a4 a5 b1 c2 vrefdig e3 clock e2 data e1 d2,d3 d5 b2 v ccd d1 swport loopsw cpout v cc(vco) lo1 lo2 lna
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 4 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 6. pinning information 6.1 pinning 6.2 pin description fig 2. ball con?guration 001aaf443 tea5766uk transparent top view e d c a b 246 135 bump a1 index area table 3. pin description symbol pin description cpout a1 charge pump output of synthesizer pll loopsw a2 switch output of synthesizer pll loop ?lter lo1 a3 local oscillator coil connection lo2 a4 local oscillator coil connection v cc(vco) a5 voltage controlled oscillator (vco) supply voltage v cca a6 analog supply voltage swport b1 software programmable port output intx b2 interrupt output gnda b5 analog ground rfin1 b6 rf input 1 freqin c1 input for 32.768 khz reference frequency busen c2 ? i 2 c-bus enable input ? spi-bus chip select input gnd(rf) c5 rf ground rfin2 c6 rf input 2 v ccd d1 digital supply voltage gndd d2 digital ground gndd d3 digital ground iss d5 i 2 c-bus or spi-bus selection input [1] tmute d6 time constant capacitor connection for soft mute data e1 input/output and control interface data line clock e2 control interface clock line input vrefdig e3 digital reference voltage for control interface
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 5 of 59 nxp semiconductors tea5766uk stereo fm radio + rds [1] the iss pin the bus type can be selected, see section 10.1 . 7. functional description 7.1 low noise rf ampli?er the low noise ampli?er (lna) input impedance together with the lc rf input circuit de?nes an fm band ?lter. the gain of the lna is controlled by the rf automatic gain control (agc) circuit to prevent overdrive of the subsequent circuits. 7.2 fm mixer the fm quadrature mixer converts the received rf (76 mhz to 108 mhz) to the if of 225 khz. downconversion is achieved by multiplication of the rf with the local oscillator (lo) frequency. image frequency suppression is achieved by using quadrature signal processing. 7.3 vco the lc tuned vco provides the local oscillator signal for the downconversion of the rf signal to if. the vco is tuned to the double frequency required for the downconversion. the lo is divided by two to provide the quadrature oscillator signals for the downconversion process. the vco frequency range is from 150 mhz to 217 mhz. integrated varactors are used for the vco tuning. the only external component used for the vco is a coil. 7.4 reference frequency an external 32.768 khz reference frequency is used as system clock. the reference clock speci?cations are given in section 13.2 . the reference frequency is used for: ? synthesizer pll reference frequency ? timing for the if counter ? adjustment of the 38 khz vco for the stereo decoder ? auto alignment of the selectivity as well as the demodulator ?lters ? auto alignment of the 57 khz rds ?lter 7.5 tuning system the pll synthesizer tuning system is suitable to operate with a 32.768 khz reference frequency. a 14-bit word is used to tune the radio, see t ab le 15 . calculation of this 14-bit word shall be done as follows: mpxout e4 multiplex signal (mpx) output vafl e5 left audio output vafr e6 right audio output table 3. pin description continued symbol pin description
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 6 of 59 nxp semiconductors tea5766uk stereo fm radio + rds formula for high-side injection: (1) formula for low-side injection: (2) where: n dec = decimal value of pll word f rf = wanted tuning frequency (hz) f if = intermediate frequency of 225 khz f ref = reference frequency of 32.768 khz example for receiving a channel at 100.1 mhz: (3) value 12246.704, is rounded down to the lowest integer value, being 12246, the pll word becomes 2fd6h. the result found using equation 1 or equation 2 must always be rounded to the lowest integer value (truncation). via the control interface this value can be written to register frqset and the tea5766uk will then start an autonomous search beginning at this frequency or go to a preset channel at this frequency. when the application is built according to the application diagram of figure 21 and with the preferred components, the tuning system will settle to the new frequency within 40 ms. the pll is triggered by writing one of the four bytes of the frqset and tnctrl and registers. the lock detect (ld) bit in register tunchk will be set after pll lock detection (see t ab le 18 ). 7.6 band limits the tea5766uk can be switched to the japanese fm band or the us/europe fm band. bit blim in register tnctrl (see t ab le 16 ) set to logic 0 enables the us/european band (87.5 mhz to 108 mhz) and blim set to logic 1 enables the japanese band (76 mhz to 90 mhz). 7.7 rf agc the rf agc (or wideband agc) prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. default the rf agc is on and it can be turned off via the control interface. the tea5766uk also has an in-band agc to prevent overloading by the wanted channel itself. the in-band agc is always on. n dec 4f rf f if + () f ref -------------------------------------- = n dec 4f rf f if C () f ref ------------------------------------- - = n dec 4 100.1 10 6 225 10 3 + () 32768 ------------------------------------------------------------------------ 12246.704 ==
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 7 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 7.8 if ?lter fully integrated if ?lter with a center frequency of 225 khz. 7.9 fm demodulator fully integrated fm quadrature demodulator. 7.10 if counter 7.10.1 if counter correct channel checking the received rf signal is converted down to a 225 khz intermediate frequency (if). the if is measured by means of a frequency counter. a correct if frequency measurement result indicates that the radio is tuned to a valid channel and not to an image or a channel with high interference. the 7-bit if counter output can be read via the control interface. the if counter is continuously active and can be read at any time via the bus. it also activates a ?ag when the if count result is outside the if count valid result window; see also section 8.2.4 . 7.10.2 if counter count time before a tuning cycle is initiated the if count period can be set to 2 ms or to 15.6 ms with bit ifctc in register tnctrl (see t ab le 16 ). when the if count period is set to 2 ms, initiating the tuning algorithm with a preset (sm = 0) will always give an rds update as shown in section 7.21 . in case the if count time is set to 15.6 ms the tuning ?owchart of section 7.20 is used. once tuned, the if count period is always 15.6 ms. 7.11 level voltage generator and level analog-to-digital converter the level voltage re?ects the received ?eld strength at the antenna. the analog level voltage is digitized to 4 bits by the level analog-to-digital converter (adc). this level adc is continuously active and the output can be read at any time via the control interface. the level adc information is used during search as well as preset tuning to compare the received signal strength with a search stop level (see section 8.2.5 ). a ?ag will be set to indicate that the level voltage is reduced below a programmable threshold value (see section 8.2.5 ). the threshold value is relative to the search stop level. the hysteresis between the search stop level and the threshold level can be selected by bit lhsw (see t ab le 19 , t ab le 20 and section 8.2.5 ). when the adc level is set to its minimum value 3, the search algorithm will only stop at channels having an rf level higher than or equal to adc level 3. after completing the search algorithm and being tuned to a station, due to the hysteresis the effective limit will be set to 0. this means that the continuous adc level check will never set the levflag. 7.12 mute 7.12.1 soft mute the low-pass ?ltered level voltage drives the softened attenuator. at low rf input levels, the audio output is faded and hence also the noise. the softened function can be turned on/off via the control interface, bit smute in register tnctrl (see t ab le 16 ).
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 8 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 7.12.2 hard mute with the mu bit of the tnctrl register byte 2 (see t ab le 16 ), the audio outputs vafl and vafr can be hard-muted; this means they are put in high-impedance state. the same can be done by setting the bits left hard mute (lhm) or right hard mute (rhm) in register testreg (see t ab le 19 ), which mute only one output at a time (or both when both set). when one output is muted the stereo decoder switches to mono. when he tea5766uk is in standby mode the audio outputs are in high-impedance state (see t ab le 4 ). 7.12.3 audio frequency mute (afm) with the afm bit of the tnctrl register byte 1, the audio signal can be muted. the audio pins maintain their functional impedance and dc-biasing level while the audio signal is muted. the audio frequency mute is automatically activated during preset as well as search tuning modes as shown in the ?owchart of figure 4 . the audio frequency mute can be disabled in software test mode when bit tm = 1 and bit afmdis = 1. 7.12.4 speci?cation of mute modes 7.13 mpx decoder the stereo decoder pll is adjustment free. the stereo decoder can be switched to mono via the control interface. 7.14 signal depending mono/stereo blend (stereo noise cancellation) with decreasing rf input level the mpx decoder blends from stereo to mono to limit the output noise. the continuous mono-to-stereo blend can also be programmed via the control interface to an rf level depending switched mono to stereo transition. stereo noise cancellation can be switched on or off via the control interface using bit snc in register tnctrl (see t ab le 16 ). when stereo noise cancellation is switched off, the radio switches from mono to stereo instead of blending. the rf input voltage where blending starts can be switched with bit snclev in register testreg (see t ab le 19 ). 7.15 software programmable port one software programmable port swport (cmos output) is available and can be controlled via the control interface. with bit swpm = 1 the software port (pin swport) functions as the output for the frrflag and with bit swpm = 0 the software port output follows bit swp. bits swp and swpm are in register tnctrl (see t ab le 16 ). in software table 4. speci?cation of mute modes type description vafl vafr impedance mode impedance mode afm audio frequency mute 350 w muted 350 w muted rhm right hard mute 350 w mono audio > 500 k w muted lhm left hard mute > 500 k w muted 350 w mono audio mu hard mute > 500 k w muted > 500 k w muted standby standby > 1 m w ->1m w - smute soft mute rf sensitive audio level; has no in?uence on mute pin or impedance
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 9 of 59 nxp semiconductors tea5766uk stereo fm radio + rds test mode the software port outputs signals according to t ab le 21 . software test mode is selected by setting bit tm of register testreg (see t ab le 19 ). the software port is not disabled by the pupd bits (see section 7.16 ). 7.16 standby mode with the pupd[1:0] (power-up/power-down) bits the radio can be put in standby mode. standby mode is de?ned as where the tea5766uk has all supply voltages available but the circuits are powered down via software (pupd) or after power-on reset. the rds part can be turned off separately, using one of the pupd bits. after a power-on reset or when the tea5766uk is in standby mode, the tea5766uk is still accessible via the control interface, but takes only a limited amount of power from the supply. the software programmable port maintains active to allow peripheral devices to be controlled. the audio outputs are hard-muted. in i 2 c-bus mode when pin busen = high and the circuits are powered down via software (pupd) the tea5766uk is in sleep mode. in this sleep mode the tea5766uk is accessible via the bus, but the radio part is not active. the i vrefdig current is higher than in standby mode. when the supply voltages v cca and v ccd are made 0 v and pin vrefdig = high, all i/os, the audio outputs and the reference clock input are in high-impedance state. the power supplies can be switched on in any order. 7.17 power-on reset after start-up of v cca and v ccd , a power-on reset circuit will generate a reset pulse and the registers will be set to their default values as shown in t ab le 12 . the power-on reset is effectively generated by v ccd . power-on reset: the audio output pins are in high-impedance state (hard mute) and all other bits are set default according to the tables in section 11 . to initialize the tea5766uk all bytes have to be transferred. 7.18 rds/rbds demodulator fully integrated rds/rbds demodulator, uses the reference frequency (32678 hz) of the pll synthesizer tuning system. the rds demodulator recovers and regenerates the continuously transmitted rds or rbds data stream of the multiplex signal (mpxrds) and provides the signals clock (rdcl), data (rdda) for further processing by the integrated rds decoder.
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 10 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 7.19 rds/rbds decoder the rds decoder provides block synchronization, error correction and ?ywheel function for reliable extraction of rds or rbds block data. different modes of operation can be selected to ?t different application requirements. availability of new data is signalled by bit davflg and output pin intx, which generates an interrupt. up to two blocks of data and status information are available via the i 2 c-bus in a single transmission. the behavior of the davflg is described in section 9 . 7.20 auto search and preset mode in search mode tea5766uk can search channels automatically. when the intx signal is used as an interrupt to the host processor to indicate a search stop, the intmsk register must be reset and only bit frrmsk must be set. in this way the host processor will only be interrupted when the search/preset algorithm is ready. search mode is initiated setting the sm bit to logic 1 in the frqset register. when bit sud is logic 0 then it searches down and when sud is logic 1 it searches up. the tuner starts searching at the frequency where it is or at a new start frequency programmed to the tuner. with the search stop level (ssl[1:0]) bits the minimum ?eld strength of channels to be found can be set. the tuner will stop on a channel with a ?eld strength equal to or higher than this reference level and then will check the if frequency. when both are valid the search mode stops. if the level check or the if count fails, it continues the search. when no channels are found the tea5766uk stops searching when it has reached the band-limit and bit blflag goes to logic 1. a search always stops with bit frrflag being set and a hardware interrupt. figure 4 shows this procedure. after this interrupt the tea5766uk will keep its status and will not update the intreg, frqchk and tunchk tuner registers for a period of 15.6 ms. the state of the tea5766uk can be checked by reading tuning registers: intreg, frqchk and tunchk. t ab le 5 shows the possible states after an auto search or a preset. a preset is done by setting bit sm to logic 0 and writing a frequency to byte frqsetmsb. the tuner jumps to the selected frequency and sets bit frrflag when it is ready. after this interrupt the tea5766uk will keep not update the tuner registers for a period of 15.6 ms. the state of the tea5766uk can be checked by reading registers: intflag, frqchk and tnctrl. t ab le 5 shows the possible states after an auto search or preset. table 5. tuner truth table [1] bit comment ifflag blflag frrflag 0 0 0 this cannot occur if intx has gone low and only ifmsk, frrmsk and blmsk were set 0 0 1 channel found during search/preset frrmsk set 0 1 0 not a valid state 011a v alid channel found and the band limit has been reached during a search; blmsk or frrmsk set 1 0 0 not a valid state
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 11 of 59 nxp semiconductors tea5766uk stereo fm radio + rds [1] this table is valid until 31.25 ms after the tuning cycle has completed. it shows the outcome of the ?ag register when a read is done after intx has gone low with the condition that no other mask bits are set than shown in the table. 7.20.1 auto high-side and low-side injection stop switch the channel quality can sometimes be improved in case of image frequency interference. this can be achieved if the local oscillator (lo) injection is positioned at the opposite side of the wanted channel (see figure 3 ). indication for image frequency interference can be derived from the if frequency counter. to enable this feature the ahlsi bit must be set to logic 1. the search/preset algorithm will stop and generate an interrupt event after the detection of a valid rssi level in combination with a frequency outside the if frequency window. the host processor can detect this state by reading the interrupt register. swap of the lo injection is achieved by inversion of bit hlsi in combination with a new tuning word for the changed oscillator frequency (see section 7.5 ). 7.20.2 muting during search or preset during preset and search the tuner is always muted, which is done by the algorithm itself. when the ahlsi bit is set and the tuner has stopped during a preset or a search because of a wrong if count, the tuner keeps muted and generates an interrupt event. in this way the host processor can switch the high or low setting quietly and waits for the new result. all these mute actions are done by blocking the audio signal and the audio output will keep its dc level and stay in low-impedance state i.e. 50 w (see t ab le 4 ). a hard mute with the mu bit will cause a plop. 101a preset or search has been done, but the wanted channel has a valid rssi level but fails the if count; when ahlsi was set hlsi must be toggled and a new pll value must be programmed; frrmsk set 1 1 0 not a valid state 1 1 1 band limit is reached during search; no valid channel found; blmsk or frrmsk set table 5. tuner truth table [1] continued bit comment ifflag blflag frrflag fig 3. switch lo from high-side injection to low-side injection using the hlsi bit 001aab460 image on high-side wanted channel switch lo from high-side to low-side image on low-side
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 12 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 7.21 rds update or alternative frequency jump a channel which transmits rds data can have alternative channels which carry the same information. these alternative channel frequencies are in the rds data, so the host processor can read the alternative frequencies and store them in a memory. more details on this subject can be found in section 3.5 of rds: the radio data system, dietmar kopitz and bev marks . fig 4. flowchart auto search or preset 001aaf444 mute the audio outputs blflag = 0 frrflag = 1 no mute reset flags set pll frequency increment current_pll by 100 khz decrement current_pll by 100 khz wait for pll to settle set levflag true false level ok start true false if ok true false ahlsi false search up true true false band limit true false search mode blflag = 0 frrflag = 1 mute blflag = 1 frrflag = 1 no mute
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 13 of 59 nxp semiconductors tea5766uk stereo fm radio + rds the tuner can do an rds update. this is a preset, but with a 2 ms if count time. the tuner will jump to the alternative frequency and check the level and the if count using a 2 ms count time. when rssi level check is above the speci?ed level and the if count result is within the limits then the tuner will stay at the alternative frequency and stay muted. the host processor can now decide what to do. if the alternative frequency is not valid it will jump back to the frequency it came from. the algorithm will ?nish with the frrflag being set and generate an interrupt. after this interrupt the tea5766uk will not measure the if count for a period of 15.6 ms. 15.6 ms after completing an rds jump a measurement of the if count will start and hence the if count result and the ifflag will be updated 31.25 ms after completing the algorithm. the level measurement will start 15.6 ms after the tuning algorithm, so bit levflag and the rssi information will be updated 15.6 ms after the algorithm. the state of the tea5766uk can be checked by reading registers: intflag, frqchk, ifchk and levchk. t ab le 6 shows the possible states after an rds update and figure 5 shows the ?owchart. 7.21.1 muting during rds update an rds update (af jump) is always muted. there are two states after the algorithm has stopped: 1. the tuner jumps to an alternative frequency which is not valid (according to the speci?ed ssl limit and ?xed if counter limits) and jumps back, then it will get not muted automatically. 2. the tuner jumps to a valid alternative frequency and stays there. now it remains in mute. the host processor can switch to not muted or it keeps the tuner muted and can check for the presence of rds data. the recommended method to get not muted is to do a preset to the current frequency (at a preset an if count time of 15.6 ms is used, which gives a more accurate if count result than the result obtained by the af jump, where 2 ms is used). [1] this table is valid until 31.25 ms after an rds update has completed. it shows the outcome of the ?ag register when a read is done after intx has gone low with the condition that no other mask bits are set than shown in the table. table 6. rds update truth table [1] bit comment ifflag blflag frrflag 0 0 0 this cannot occur if intx has gone low and only ifmsk, frrmsk and blmsk were set 0 0 1 alternative frequency jump successful; radio is tuned to the alternative frequency and keeps muted 0 1 0 not a valid state 0 1 1 not a valid state 1 0 0 not a valid state 101af jump has been done, but the wanted channel fails the if count, the pll will be set back to the old value 1 1 0 not a valid state 1 1 1 this cannot occur if intx has gone low and only ifmsk, frrmsk and blmsk were set
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 14 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 8. interrupt handling 8.1 interrupt register the ?rst two bytes of the i 2 c-bus register contain the interrupt masks and the interrupt ?ags. a ?ag is set when it is logic 1. fig 5. flowchart rds update 001aab462 activate mute store 'old' pll setting clear levflag clear ifflag set pll to af frequency frrflag = 1 blflag = 0 keep mute (pll is af frequency) frrflag = 1 blflag = 0 not mute (pll is old frequency) wait for pll to settle set levflag true false level ok wait for if counter reset 'old' pll setting false true if ok wait for pll to settle start set if count time to 2 ms table 7. intflag (intreq byte 1) - i 2 c-bus register byte 0r bit allocation 7 6 5 4 3 2 1 0 davflg testbit lsyncfl ifflag levflag - frrflag blflag table 8. intmsk (intreq byte 2) - i 2 c-bus register byte 1r/byte 0w bit allocation 7 6 5 4 3 2 1 0 davmsk - lsyncmsk ifmsk levmsk - frrmsk blmsk
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 15 of 59 nxp semiconductors tea5766uk stereo fm radio + rds the interrupt ?ag register contains the ?ags set according to the behavior outlined in section 8.2 . when these ?ags are set they can also cause the intx to go active (hardware interrupt line) depending on the status of the corresponding mask bit in t ab le 8 . a logic 1 in the mask register enables the hardware interrupt for that ?ag. hence it is conceivable that, with all the mask bits cleared, the software could operate in a polling mode by a continuous read operation of the interrupt ?ag register to look for bits being set. interrupt mask bits are always cleared after reading the ?rst two bytes of the interrupt register. this is to control multiple hardware interrupts (see figure 6 ). bit lsyncmsk has a different function and is not cleared after reading the interrupt register bytes (see section 8.2.3 ). 8.1.1 interrupt clearing the interrupt ?ag and mask bits are always cleared after: ? they have been read via the control interface ? a power-on reset 8.1.2 timing the timing sequence for the general operation interrupts is shown in figure 6 and shows a read access of the interrupt bytes intflag and intmsk and a subsequent (though not necessarily immediate) write to the mask register. it also indicates two key timing points a and b. if an interrupt event occurs while the register is being accessed (after point a) it must be held until after the mask register is cleared at the end of the read operation (point b). point a is situated after the r/w bit has been decoded and point b is where the acknowledge has been received from the master (host processor, etc.) after the ?rst two bytes have been sent. the low time for the intx line (t p ) has a maximum value speci?ed in section 13.4 . however it can be shorter if the read of the intreg registers occurs within the t p . 8.1.3 reset a reset can be performed (at any time) by a simple read of the interrupt bytes (byte 0r and byte 1r), which automatically clears the interrupt ?ags and masks.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 16 of 59 nxp semiconductors tea5766uk stereo fm radio + rds (1) interrupt events that occur outside of the region a-b set their respective ?ag bits in the normal way immediately and can th us trigger a hardware interrupt if the mask bits are set. (2) the blocking of interrupts is marked by the region a-b 1 / b 2 depending on the actual read cycle. b 1 is when only the intflag is read and a stop condition is received (only intflag is read so only this will be cleared). b 2 is when both registers are read and hence cleared and this is terminated by either an acknowledge or stop bit. (3) interrupt events that occur between a and b set their respective ?ags after the mask bits are cleared. which means that in this diagram an interrupt e vent occurred in period a-b, so after a-b the ?ag goes to logic 1. (4) all interrupt mask bits are cleared after the interrupt ?ag and mask bytes are read. (5) software writes to the mask byte and enables the required mask bits. any ?ags currently set will then trigger a hardware int errupt. (6) intx is set high (inactive) after the interrupt mask bytes are read. fig 6. i 2 c-bus interrupt sequence, read and write operation 001aab464 device address intflag intmsk read access data intmsk frqsetmsb frqsetlsb write access sr ack interrupt event interrupt flag bit 0r data ack a (1) (2) (3) interrupt mask bit (4) (5) (6) (5) b 1 b 2 1r data ack data ack device address s p w ack 0w data ack 1w data ack 2w data ack intx
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 17 of 59 nxp semiconductors tea5766uk stereo fm radio + rds (1) interrupt events that occur outside of the region a-b set their respective ?ag bits in the normal way immediately and can th us trigger a hardware interrupt if the mask bits are set. (2) effectively interrupts are enabled at the ?rst falling edge of scl after cs has gone high. (3) interrupt events that occur between a and b set their respective ?ags after the mask bits are cleared, if the cause for the interrupt is still present at point b. (4) all interrupt mask bits are cleared after the interrupt ?ag and mask bytes are read. (5) software writes to the mask register and enables the required mask bits. any ?ags currently set will then trigger a hardware interrupt. (6) intx is set high (inactive) after the interrupt ?ag and mask register are read. fig 7. spi-bus interrupt sequence, read and write operation 001aaf445 intflag intmsk mosi cs r/ w interrupt event interrupt flag bit data a (1) (2) (3) interrupt mask bit (4) (5) (6) (5) b data subaddress subaddress intflag intmsk r/ w data data intx
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 18 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 8.2 interrupt ?ags and behavior 8.2.1 multiple interrupt events if the interrupt mask register bit is set then the setting of an interrupt ?ag for that bit causes a hardware interrupt (intx goes low). if the event occurs again before the ?ag is cleared, then this does not trigger any further hardware interrupts until that speci?c ?ag is cleared. however two different events can occur in sequence and generate a sequence of hardware interrupts. only when read, followed by a write of the intmsk byte has been done, a second interrupt can be generated, as the ?rst interrupt blocks the input of the intx one-shot generator. if subsequent interrupts occur within the intx low period then these interrupts do not cause the intx period to extend beyond its speci?ed maximum period. see also section 8.3 , figure 8 . 8.2.2 data available: davflg when a new block of data is received, the davflg is set according to the diagrams shown in section 9 where the different dav modes are described. once synchronized, this continues for all subsequent received blocks (dependent on dav mode) and in the following situations: ? during synchronization search in any dav mode, if two valid blocks in the correct sequence are received with bbc < bbl (synchronized) ? during synchronization search in dav-b mode if a valid a(c)-block has been detected; this mode can be used for fast search tuning (detection and comparison of the program identi?cation (pi) code contained in the a(c)-block) ? if the pre-processor is synchronized and in mode dav-a or dav-b a new block has been processed ? if the pre-processor is synchronized and in dav-c mode two new blocks have been processed ? if the decoder is synchronized and for any dav mode, with lsyncmsk = 0, loss of synchronization is detected (?ywheel loss of synchronization, resulting in a restart of synchronization search) the davflg is reset by a read of bl[7:0] of rdsr2 (byte 15r) or bp[7:0] of rdsr3 (byte 17r). an interrupt is given each time when a new block of data is decoded and when the davmsk is set; for details see section 9 . 8.2.3 rds synchronization: lsyncfl the sync bit, (see t ab le 22 ) shows the status of the rds decoder. if it is set the decoder is synchronized. the action of the tea5766uk depends on the status of the lsyncmsk bit in t ab le 8 . if this is set then the loss of synchronization causes the lsyncfl to go logic 1 and a hardware interrupt is generated. the rds part of the tea5766uk is set to idle and waits for the host processor to initiate a new synchronization search by setting the nwsy bit as described in t ab le 26 .
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 19 of 59 nxp semiconductors tea5766uk stereo fm radio + rds if the lsyncmsk bit is logic 0 and synchronization is lost the tea5766uk automatically starts a new synchronization search. it will not generate a hardware interrupt. the host processor can wait until the rds decoder is synchronized again; this will be indicated by the davflg and the sync status bit (this requires the davmsk being set). the lsyncfl is reset by a read of the intmsk byte 1r. the lsyncmsk is not reset by a read of the intmsk byte; it must be set or reset by the host processor. resetting it automatically would change the status of the tea5766uk and cause an automatic synchronization search as described above. how the synchronization is de?ned is explained in en 62106 speci?cation of the radio data system (rds) for vhf/fm sound broadcasting range from 87.5 to 108 mhz, 1998 and in brief in section 9 . 8.2.4 if frequency: ifflag during automatic frequency search, preset or af update, the fm part of the tea5766uk performs a check on the received if frequency as a measure of the level of interference in the channel received. if an incorrect if frequency is received then this indicates the presence of strong interferers or tuning to an image and the ifflag bit in the intflag register is set. also a preset to a channel with no signal will result in a wrong if count value and hence setting of the ifflag. when a search, preset or af update is ?nished the frrflag will be set to indicate this and generates an interrupt. the host processor can now read the outcome of the registers which will contain the if count value and the ifflag status of the channel it is tuned to. in case of an af update the if count value of the alternative frequency will be in the registers, also when it jumps back because it will then not start a new if count. note: 15.6 ms after the tuning algorithm has been completed the if counter will start a new count. so 31.25 ms after a failed af update the if count result will be equal again to that of the channel from where the jump was initiated. 15.6 ms after the frrflag has been set the if counter will start to run continuously on the tuned frequency and if the conditions for correct frequency are not met then this sets the ifflag bit in the interrupt register. when the ifmsk is set this will also cause an interrupt. the ifflag bit is cleared by a read of byte 1r, or by starting the tuning algorithm. 8.2.5 rssi threshold: levflag the level voltage re?ects the ?eld strength received by the antenna. the level voltage is analog to digital converted with 4 bits and output via the bus. this 4-bit level value can be compared to a threshold level set by the ssl bits in t ab le 16 or the lhsw bit in t ab le 19 . the level adc (which converts the analog value to digital) can be triggered to convert in two ways. during a tuning step, a search, a preset or an af update the levflag is triggered by these algorithms and compares the level with the threshold set by the ssl bits. the levflag bit is set if the rssi level drops below the threshold level set by the ssl bits in t ab le 16 the hardware interrupt is only generated if the corresponding mask bit is set.
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 20 of 59 nxp semiconductors tea5766uk stereo fm radio + rds after a search, a preset or an af update the threshold for comparison is switched to the hysteresis level. the hysteresis level is set by the combination of ssl bits and the lhsw bit, which results in a hysteresis as shown in t ab le 20 . then the level adc starts to run automatically and compares the level each 500 m s with the hysteresis level. the levflag bit is set if the rssi level drops below the threshold level set by the ssl bits in combination with the lhsw bit. the hardware interrupt is only generated if the corresponding mask bit is set. with the lhsw bit a small or a large hysteresis can be selected, which results in the levels of the left rssi hysteresis threshold column for lhsw = 0 and in the right rssi hysteresis threshold column (see t ab le 19 ). remark: when a search or preset is done with the adc level set to 3 then when the algorithm has ?nished, the threshold level is set to 0. hence the levflag will never be set. the levflag bit is cleared by a read of the intmsk byte 1r, or by starting the tuning algorithm. 8.2.6 frequency ready: frrflag the frequency ready ?ag bit is set when the automatic tuning has ?nished a search, a preset or an rds af update. the function of this bit is described in t ab le 5 and t ab le 6 . the frrflag is cleared by a read of byte 1r. 8.2.7 band limit: blflag the band limit bit blflag is set when the automatic tuning has detected the end of the tuning band or when the pll cannot lock on a certain frequency. the description of this bit is in t ab le 5 and t ab le 6 . this bit is cleared by a read of byte 1r. 8.3 interrupt line: pin intx the interrupt line driver is a mos transistor with a nominal sink current of 900 m a, it is pulled high by an 18 k w resistor connected to pin vrefdig. the interrupt line can be connected to another similar device with an interrupt output and an 18 k w pull-up resistor, providing a wired-or function. this allows any of the drivers to pull the line low by sinking the current as speci?ed in section 13.4 . so when a ?ag is set and not masked it generates an interrupt.
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 21 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 9. rds data processing the rds demodulator and decoder perform the following operations: ? demodulation of the rds/rbds data stream from the mpx signal ? symbol decoding ? obtain block and group synchronization ? error detection and correction ? store last and previous data block received with associated id and error status ? set the davflg when new data is received ? set the sync status bit according to the current synchronization state ? set the lsyncfl ?ag when synchronization is lost the rds decoder can be set in different modes, each meant to look for speci?c information. the modes dav-a, dav-b and dav-c are described in the next paragraphs. 9.1 dav-a processing mode the dav-a processing mode is the standard processing mode. in this mode each time when a data block has been decoded it is transferred to the bus registers. it generates interrupts on the intx line after every new block of rds data that has been processed and also the davflg is set. this is shown in figure 9 . the davflg is reset by a read of the bus registers. (1) flag is set immediately after the reset, because event is still present. (2) when ?ag is set next interrupts are blocked until read or write intmsk. (3) when ?ag a is set, the interrupt is not extended beyond 10 ms. (4) read intmsk clears ?ag, intmsk and intx. (5) write intmsk enables intx. fig 8. interrupt line behavior 001aaf446 flag b (1) intx read intmsk (4) 10 ms < 10 ms read clears intx (3) write intmsk (5) flag a (1) (2) v cc interrupt event 10 ms < 10 ms
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 22 of 59 nxp semiconductors tea5766uk stereo fm radio + rds if a data block is decoded and a new data block arrives, intx will go low again, the davflg will be set, the last block will be shifted to the previous block and the last decoded block will be put in the last block. this means that all rds data is still available in the bl and bp registers. when the bus registers are not read the davflg will not be reset. if a data block is decoded and a new data block arrives, intx will go low and the last block will be shifted to the previous block and the last decoded block will be put in the last block. this means that all rds data is still available in the bl and bp registers, but must be read. this is indicated by the dovf bit which is set. if again the bus registers are not read, data will be lost except when this read is done within 20 ms after the intx line has gone low, so 2 ms before the arrival of a new block. if this read is done at least 2 ms before the arrival of a new block, then bl and bp are read and the data in the decoder buffer is then instantaneously shifted to the bl register. all data is now read and the dovf bit will be reset. the diagram assumes that block synchronization has been achieved and that no other interrupt ?ags are being set.
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 23 of 59 nxp semiconductors tea5766uk stereo fm radio + rds (1) bit dovf set when 2 new blocks received in bl and bp registers. (2) instant copy of decoder buffer to bl register and bl to bp register after reading register rdsr4. the block in bl is considered as a new block. (3) in order not to lose d 1 a read must be performed before d 1 enters decoder buffer, thus read ?nishes within 21 ms after dovf set to logic 1. (4) dovf is cleared when the bl register is read. to be of use, dovf has to be read before bl and bp registers. (5) to prevent dovf being set again, an extra read of bl must be performed before a2 has been decoded. fig 9. dav-a timing diagram 001aaf587 a 1 21.9 ms davflg davflg set on falling edge of davn signal, cleared on read bl register intx b 1 read bl end read intmsk read intflg + rds on intx t p read time bus registers bl register a 1 bp register t p 10 ms read bl read bl c 1 d 1 a 2 b 2 c 2 b 1 (1) (2) (3) (4) (1) (5) c 1 d 1 b 2 xa 1 b 1 c 1 a 2 being decoded b 1 in the decoder buffer dovf (data overflow) bit c 1 d 1 a 2 a 1 b 1 c 1 d 1 c 1 b 1 a 2 d 1 a 2 d 1 a 2 a 2 b 2 a 2 b 2 a 1 decoder registers 9.98 ms 9.98 ms > 2 ms
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 24 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 9.2 dav-b processing mode and fast pi search mode this mode is used when, for example, the receiver has been re-tuned to a new station and a fast search of the pi code (always contained in the a/c-block) is required. the diagram shown in figure 10 , assumes that the rds decoder is unsynchronized initially and is performing a synchronization search. during synchronization search the decoder does not set the davflg until a valid a/c-block is detected. if a valid b-block is immediately detected, the decoder is synchronized and the sync bit is set to logic 1. in fact, if any 2 good blocks in a valid order are found the rds decoder will synchronize and give an interrupt. if for some reason a valid b block was not received the next valid a/c-block is decoded and the davflg set. the bp and bl registers would record the a-block history. after synchronization each decoded block will set the davflg (assuming it was reset by a read action) and generate an interrupt. bbg = 3: synchronization is reached after receiving 1 good block and after 0, 1 or 2 bad blocks and again a good block. after three bad blocks there will be no synchronization and the counters will be reset waiting for a new good block. fig 10. dav-b timing diagram 001aaf588 b 1 21.9 ms only valid blocks with no errors are counted as good blocks error correction applied according to sym bits bad good good good bad read bl register read intmsk not synchronized synchronized davflg intx sync status bit good a or c' block detected bad c' 1 bus access - read d 1 a 2 b 2 c 2 bl register x bp register c' 1 c' 1 c' 1 b 2 c 2 xxxxc' 1 b 2
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 25 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 9.3 dav-c reduced processing mode the dav-c processing mode is very similar to dav-a mode with the main exception that a data ?ag is only set after two new blocks are received. hence the update rate is reduced by half. (1) b 1 is copied to the bl register shortly before c 1 is decoded. (2) davflg cleared at end read bp register and forced to zero till end read of rdsr4. (3) intx cleared at end read intmsk. (4) bl register copied to bp register and c 1 to bl register. fig 11. dav-c timing diagram case 1, normal 001aaf447 a 1 21.9 ms b 1 t p interrupt read t read davflg being decoded (1) (2) (3) (4) read access (case 1) intx c 1 d 1 a 2 b 2
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 26 of 59 nxp semiconductors tea5766uk stereo fm radio + rds (1) two new blocks have arrived in the bl and bp register. (2) instant copy c 1 from decoder buffer to bl and bl to bp just before d 1 decoded due to read action. (3) instant copy of a 2 from decoder buffer to bl and bl to bp. (4) davflg not cleared as no read is performed. (5) davflg is reset when ?rst new block would have been copied to bl register. (6) davflg is set when second new block is in decoder buffer. (7) no read on intx, b 1 will be lost. (8) dashed line shows what would happen if no read occurred at (a). dovf bit set until the next read of bp register, however d 1 and a 2 would be lost. (9) two new blocks have arrived in bl/bp (c 1 , d 1 ) and a new block (a 2 ) has entered the decoder buffer. hence dovf is set again. to prevent this, an extra read must be performed after reading (a). fig 12. dav-c timing diagram case 2, late read of bl and bp register 001aaf448 a 1 21.9 ms b 1 (a) t read t p = 10 ms intx (1) (3) (4) (5) (7) (8) (9) (6) (2) read access (case 2) dovf (data overflow) bit c 1 d 1 a 2 b 2 bl register a 1 bp register d 1 c 1 a 2 d 0 d 0 c 0 c 1 a 1 d 1 davflg (case 2)
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 27 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 9.4 synchronization 9.4.1 conditions for synchronization when the rds decoder is turned on it must be synchronized to extract valid data from the mpx signal. to do so the decoder automatically initiates a search for synchronization. the conditions to meet synchronization and the status of this synchronization can be set and checked with the following bits: ? bbl[5:0] - bad blocks lose - these bits can be set via the bus and have a value between 0 and 63. ? gbl[5:0] - good blocks lose - these bits can be set via the bus and have a value between 0 and 63. ? bbg[4:0] - bad blocks gain - these bits can be set via the bus and have a value between 0 and 32. ? gbc[5:0] - good block count - these bits can be read via the bus and have a value between 0 and 63. ? bbc[5:0] - bad block count - bits can be read via the bus and have a value between 0 and 63. when the decoder is not synchronized it will initiate a synchronization search. this involves calculation of the syndrome (see en 62106 speci?cation of the radio data system (rds) for vhf/fm sound broadcasting range from 87.5 to 108 mhz, 1998 for details) for each block of 26 received bits on a bit-by-bit basis. when a correct syndrome (and hence block id) is received the decoder clocks the next 26 bits into the internal registers and performs a second syndrome check. synchronization is found when a certain number of blocks have been decoded and two goods blocks have been found; this number of blocks is de?ned by the bbg bits. if the ?rst block needed for synchronization has been found and the expected second block (after 26 bits) is an invalid block, then the decoder module internal bad_blocks_counter is incremented and the next expected block is calculated. exception: if rbds mode is selected and the ?rst block is e, then the next expected block is always block a, until synchronization is found or the maximum bad_blocks_counter value is reached. if the decoder module internal bad_blocks_counter reaches the value of the bbg[4:0], then immediately a new synchronization search (bit-by-bit) is started to ?nd a new ?rst block. the synchronization is monitored by use of two ?ywheel counters; gbc and bbc. these are 6-bit counters that can be preset by the gbl and bbl bits to values between 0 and 63. each time a block is decoded and recognized as a bad block the bbc value is incremented by 1. when the bbc value is equal to the bbl value, synchronization is lost. the sync bit will become logic 0 and the lsyncfl is set to signal the loss of synchronization. the tea5766uk will now automatically initiate a new synchronization search. each time when a good block is decoded the gbc value is incremented. when the gbc value is equal to the gbl value both counters (bbc and gbc), are set to 0 and a new count starts. the gbc counter is only incremented when the decoder is synchronized.
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 28 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 9.4.2 modi?ed mobile broadcast service (mmbs) mode there are three synchronization modes, rds, rbds and mmbs. ? rds mode: the decoder can read a, b, c and d blocks and synchronize on a, b, c and d blocks. ? rbds mode: the decoder can read a, b, c, d and e blocks and synchronize on a, b, c and d blocks. ? mmbs mode: the decoder can read a, b, c, d and e blocks and synchronize on a, b, c, d and e blocks. mmbs mode can be selected using bit mmbs in register testreg (see t ab le 19 ). 9.4.3 data over?ow during synchronization after rds data is read from the registers, new available blocks are shifted to the registers as described in section 9.1 to section 9.3 . when the registers are not read in time, the decoder cannot shift any new available block to the registers and hence a data over?ow will occur; this is indicated by the dovf bit which is set to logic 1. the dovf bit is reset by a read of the registers or if nwsy = 1 which results in the start of a new synchronization search. 9.5 rds ?ag behavior during read action each time when an rds data block is decoded the davn signal will go low to signal the presence of a new data block. also the davn signal triggers the interrupt output intx. in principle the microprocessor must now start reading and must have read all rds data, so byte 12r to byte 19r before the arrival of a new rds data block. in the application there can be a too large delay between the arrival of a new block and reading this block. this can have various causes such as a microprocessor which has to start up from sleep mode or when polling is used instead of interrupt based read actions. figure 13 describes the behavior of the davflg and the davn signal when polling, which effectively means that reading can occur at any moment. remark: davn sets the intx one-shot generator when davmsk = 1. unlike intx, davn is not cleared by a read of the mask register.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 29 of 59 nxp semiconductors tea5766uk stereo fm radio + rds blocking davflg: at end of reading byte 15r or byte 17r (dav-a, b/c) davflg is forced to zero. only after reading byte 19r davflg is released again. if synchronous reading is performed using tea5766uk generated interrupts, this problem does not occur. to prevent unde?ned situations, byte 12r to byte 19r should always be read in one action immediately after each other. signal davn 1 intx. (1) normally reading byte 19r would reset signal davn, but now it is reset after 10 ms, the maximal low time of signal davn. (2) read of byte 15r in dav-a and dav-b mode clears davflg. in dav-c mode two consecutive rds data blocks are read and hence davf lg is reset after reading byte 17r instead of byte 15r (dotted line). (3) read of byte 19r clears signal davn. (4) write byte 0w (interrupt register). fig 13. rds ?ag behavior b a rds data davn davflg reset of davflg read byte: 15r 0r 19r 0w 17r cda b (1) (2) (3) (4) 10 ms c 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 001aab475
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 30 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 9.6 error detection and reporting the tea5766uk must report information on the number of errors corrected in the last and previously decoded blocks. this is reported in the elb[1:0] and epb[1:0] ?elds as shown in t ab le 22 . during synchronization search the error correction is disabled for detection of the ?rst block and is enabled for processing of the second block according to the mode set by the sym[1:0] bits as described in t ab le 26 . 9.7 rds data - reading from registers to read rds data the microprocessor must read byte 12r to byte 19r. all 8 bytes must be read to reset the status bytes byte 12r and byte 13r, i.e. effectively the status bits can be updated by the decoder after reading the last bit of byte 19r. the dovl bit is cleared after reading the last bit of byte 19r and the status of the sync bit does not depend on reading the register; the sync bit tells if the decoder is synchronized or not. when starting a read action from byte 12r, the decoder blocks update from the rds bytes until byte 19r has been read. rds byte 12r to byte 19r must be read in one read action. 10. control interface 10.1 selection between i 2 c-bus and spi-bus the tea5766uk supports the i 2 c-bus and the 3-wire spi-bus. with pin iss the bus types can be selected according to t ab le 9 . table 9. bus type selection pin iss bus low i 2 c-bus high spi 3-wire
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 31 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 10.2 i 2 c-bus the full i 2 c-bus speci?cation can be found in the i 2 c-bus speci?cation, version 2.1, january 2000. the i 2 c-bus speci?cation is based on version 2.1, january 2000, expanded by the following de?nitions: ? the chip has two i 2 c-bus addresses: C fm radio: 001 0000[r/ w] starts at byte 0r or byte 0w C rds part: 001 0001[r/ w] starts at byte 12r or byte 7w ? structure of the i 2 c-bus: C slave transceiver, subaddresses not used. C maximum low-level input: v il = 0.3 v vrefdig C minimum high-level input: v ih = 0.7 v vrefdig 10.2.1 data transfer to the tea5766uk ? the data transfer has to be in the order shown in figure 14 . the bit 0 (lsb) = 0 of the address indicates a write operation to the tea5766uk, indicated by the r/ w bit of the i 2 c-bus address. ? bit 7 of each byte is considered the msb and has to be transferred as the ?rst bit of the byte. ? the data becomes valid bitwise at the appropriate falling edge of the clock. a stop condition after any byte can shorten transmission times. when writing to the transceiver by using the stop condition before completion of the whole transfer: C the remaining bytes will contain the old information. C if the transfer of a byte is not completed, the new bits will be used, but a new tuning cycle will not be started. to speed up rds traf?c it is possible to read all the rds data and then only write back byte intmsk to set the appropriate mask(s) again. a. write mode b. read mode (1) s = start condition. (2) a = acknowledge (sda low). (3) nak = non acknowledge (sda high). (4) p = stop condition. fig 14. i 2 c-bus data transfer 001aaf456 chip address (read) data byte 1 s (1) a (2) a 001aaf457 chip address (write) data byte(s) s (1) nak (3) p (4) a (2)
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 32 of 59 nxp semiconductors tea5766uk stereo fm radio + rds figure 15 shows the sequence of i 2 c-bus data bytes for read and write operations for both fm and fm + rds access. for simplicity the address, start, stop and acknowledge bits are not shown. the fm and rds part have different i 2 c-bus addresses as stated. when the tea5766uk is addressed with the fm radio address, also in one read action byte 12r to byte 27r can be read. a read does not have to stop at byte 11r. when writing also all bytes, byte 0w to byte 10w can be written with one write action. so effectively using the rds part address only skips some bytes, which reduces bus access. with the standby bit, the tea5766uk can be switched in a low current standby mode. then the bus is still active. is the bus interface deactivated, by making pin busen low and without programmed standby mode, the tea5766uk keeps its normal operation, but is isolated from the bus lines. it is possible to operate the tea5766uk with pin busen hard wired to pin vrefdig and have the bus interface always active. power-on reset: the mute is set, all other bits are set default according to the tables in section 11.2 . to initialize the tea5766uk all bytes have to be transferred. 10.2.2 i 2 c-bus output driving characteristics the i 2 c-bus output driving characteristics deviate from table 4 and table 5 in ref . 1 as shown in t ab le 10 . a. fm read mode data transfer b. rds read mode data transfer c. fm write mode data transfer d. rds write mode data transfer fig 15. i 2 c-bus data transfers to the tea5766uk 001aaf458 byte 11r byte 10r byte 9r byte 8r byte 7r byte 6r byte 5r byte 4r byte 3r byte 2r byte 1r byte 0r 001aaf459 byte 23r byte 22r byte 21r byte 20r byte 19r byte 18r byte 17r byte 16r byte 15r byte 14r byte 13r byte 12r byte 27r byte 26r byte 25r byte 24r 001aaf460 byte 6w byte 5w byte 4w byte 3w byte 2w byte 1w byte 0w 001aaf461 byte 10w byte 9w byte 8w byte 7w
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 33 of 59 nxp semiconductors tea5766uk stereo fm radio + rds [1] the maximum fall time for the sda and scl bus lines quoted in table 5 of ref . 1 , 300 ns, is shorter than the speci?ed maximum for the output stages, 350 ns, therefore no series protection resistors may be connected between the sda and scl pins and the sda and scl bus lines as shown in ?gure 36 of ref . 1 . 10.2.3 i 2 c-bus timing diagram table 10. characteristics of the data output stage for fast mode and standard mode symbol parameter conditions min typ max unit v ol1 low-level output voltage open collector; i sink = 2 ma; v vrefdig >2v standard mode 0 - 0.5 v fast mode 0 - 0.5 v v ol3 low-level output voltage fast mode; open collector; i sink = 2 ma; v vrefdig <2v 0 - 0.5 v t of output fall time from v ih(min) to v il(max) ;c b = 5 pf to 100 pf [1] standard mode 250 - 350 ns fast mode 250 - 350 ns in tea5766uk, signal sda is present on pin data and signal scl on pin clock. c b = capacitive load for each bus line: < 100 pf. t f = fall time of both sda and scl signals: 20 + 0.1 c b < t f < 350 ns, where c b = total capacitance on bus line in pf. t r = rise time of both sda and scl signals: 20 + 0.1 c b < t f < 350 ns, where c b = total capacitance on bus line in pf. t hd;sta = hold time (repeated) start condition. after this period, the ?rst clock pulse is generated: > 600 ns. t high = high period of the scl clock: > 600 ns. t low = low period of the scl clock: > 1.3 m s t su;sta = set-up time for a repeated start condition: > 600 ns. t hd;dat = data hold time: 300 ns < t hd;dat < 900 ns. remark: 300 ns lower limit is added because the tea5766uk has no internal hold time for the sda signal. t su;dat = data set-up time: > 100 ns. if tea5766uk is used in a standard mode i 2 c-bus system, t su;dat > 250 ns. t su;sto = set-up time for stop condition: > 600 ns. t buf = bus free time between a stop and a start condition: > 600 ns. t su(busen) = set-up time on pin busen (bus enable): > 10 m s. t h(busen) = hold time on pin busen: > 10 m s. fig 16. i 2 c-bus timing diagram p s sr p 001aaf518 t hd;sta t buf t su;sta t su;dat t f t high t low t su;sto t r t hd;dat sda scl busen t su(busen) t h(busen)
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 34 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 10.3 spi-bus spi stands for serial peripheral interface. tea5766uk uses the spi-bus in 3-wire mode, the data-in and data-out are combined to one bidirectional data line. for this application the spi-bus works as a slave receiver or a slave transmitter. during an spi transfer, the input serial clock line spiclk is driven by the master microcontroller up to a frequency of 2.5 mhz and synchronizes shifting and sampling the information on the serial data line. the slave select line cs allows individual selection of a slave spi device. the lines of the spi-bus interface are associated to pins as shown in t ab le 11 . the tea5766uk functions as a slave receiver and slave transmitter with a maximum clock frequency of 2.5 mhz. data transfer is possible when signal cs (pin busen) is low. when pin busen is high, the clock input line is disabled internally and the serial output of the tea5766uk is in 3-state. the data transfer consists of packages of 8 bits data. first the address byte is shifted in, followed by 2 data bytes, which gives a total of 24 bits. the address byte consists of 2 null bits, 5 address bits and 1 bit (r/w) for the direction of the data transfer. the 2 null bits are added to the address byte because of the spi 8-bit data transfer protocol. bits a[4:0] are the register address. all register addresses between 0 and 15 are allowed. register addresses between 16 and 31 are not recognized and the spi-bus interface leaves the data line in 3-state. the r/w bit determines the direction of the data transfer. if r/w = 1, the slave device is set to read mode and if r/w = 0, the slave device is set to write mode. bits d[15:0] are the data bits. this data size corresponds to that of the register bank implemented in the tea5766uk. the data transfer is such that the msb is shifted ?rst and the lsb last. when pin busen becomes low, an spi start condition is detected and data is sampled in the slave device on the rising edge of the pin clock signal. after the r/w bit is shifted in, the r/w selection becomes active at the next falling edge. if r/w = 1 data will be put at the data output and shifted out on the falling edge of the clock. when pin busen becomes high, the slave device (tea5766uk) will be set to idle mode, in which the data output line is set to 3-state. a negative edge on pin busen restarts the data transfer. in figure 18 and figure 19 the spi transfer is shown. table 11. spi-bus control signals and pinning spi signal tea5766uk pin description cs busen chip select (active low) spiclk clock clock input line mosi/miso data serial data input and output of slave fig 17. spi-bus transfer 001aaf462 d0 d15 r/w a0 a1 a2 a3 a4 - -
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 35 of 59 nxp semiconductors tea5766uk stereo fm radio + rds fig 18. spi transfer, 3 wire-mode 001aaf451 - - a4 data busen clock a3 a2 a1 a0 r/w d15 d14 d13 d12 d11 to d1 d0 t spir = spi rise time: 5 ns < t spir <50ns. t spif = spi fall time: 5 ns < t spif <50ns. t spilead = spi enable lead time: > 250 ns. t spia = spi access time (slave): > 150 ns. t clcl = clock cycle time: > 400 ns. t spiclkh = spiclk high time: > 190 ns. t spiclkl = spiclk low time: > 190 ns. t spilag = spi enable lag time: > 250 ns. t spioh = spi output data hold time: > 0 s. t spidis = spi disable time (slave): 0 ns < t spidis < 167 ns. t spidsu = spi data set-up time (master or slave): > 5 ns. t spidh = spi data hold time (master or slave): > 5 ns. t spidv = spi enable to output data valid time: < 240 ns. fig 19. spi-bus timing diagram t spif t spia t spidsu t spidh t spidsu t spidh t spidv t spidh t spidis t spioh t clcl t spiclkh t spiclkl t spilead t spif t spir t spir t spilag slave msb/lsb out slave lsb/msb out not defined 001aaf452 busen (cs) clock (spiclk) data (miso output) data (mosi input) msb/lsb in lsb/msb in
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 36 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 11. registers 11.1 register map the reference for the register map is the motorola spi addressing. the actual register is in fact one long register, so the i 2 c-bus bytes are mapped onto the spi registers. [1] t ab le 13 shows how the i 2 c-bus bytes are mapped onto the spi bytes. [2] first four bits are the version bits and change with every mask set. 11.2 register description table 12. register overview register name spi address i 2 c-bus byte number r/w access reset reference read write intreg 02 0r - 1r 0w [1] r/w 0000h t ab le 14 frqset 03 2r - 3r 1w - 2w r/w 8000h t ab le 15 tnctrl 04 4r - 5r 3w - 4w r/w 08d2h t ab le 16 frqchk 05 6r - 7r r - t ab le 17 tunchk 06 8r - 9r r - t ab le 18 testreg 07 10r - 11r 5w - 6w r/w 0000h t ab le 19 rdsr1 08 12r - 13r r - t ab le 22 rdsr2 09 14r - 15r r - t ab le 23 rdsr3 10 16r - 17r r - t ab le 24 rdsr4 11 18r - 19r r - t ab le 25 rdsw1 12 20r - 21r 7w - 8w r/w 0010h t ab le 26 rdsw2 13 22r - 23r 9w - 10w r/w 0000h t ab le 27 manid 00 24r - 25r r 102bh [2] t ab le 28 chipid 01 26r - 27r r 5766h t ab le 29 table 13. spi to i 2 c-bus map for spi address 02 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spi 02 i 2 c 0r 1r/0w table 14. intreg - spi address 02 or i 2 c byte 0r + byte 1r/byte 0w bit description bit symbol access reset value description spi i 2 c 15 7 davflg r 0 1 = rds data is available 14 6 testbit r 0 internal use 13 5 lsyncfl r 0 1 = synchronization is lost 12 4 ifflag r 0 1 = if count is not correct
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 37 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 11 3 levflag r 0 outside the tuning period the rssi level is continuously checked: 1 = rssi level has dropped below adc search stop level during a tuning period (preset or search): 1 = rssi level has dropped below adc search stop level 10 2 - - 0 not used 09 1 frrflag r 0 1 = the tuner state machine is ready 08 0 blflag r 0 1 = during a search the band limit has been reached or timed out 07 7 davmsk r/w 0 masks bit davflg 06 6 - - 0 not used 05 5 lsyncmsk r/w 0 masks bit lsyncfl 04 4 ifmsk r/w 0 masks bit ifflag 03 3 levmsk r/w 0 masks bit levflag 02 2 - - 0 not used 01 1 frrmsk r/w 0 masks bit frrflag 00 0 blmsk r/w 0 masks bit blflag table 14. intreg - spi address 02 or i 2 c byte 0r + byte 1r/byte 0w bit description continued bit symbol access reset value description spi i 2 c table 15. frqset - spi address 03 or i 2 c byte 2r + 3r/byte 1w + byte 2w bit description bit symbol access reset value description spi i 2 c 15 7 sud r/w 1 1 = search up 0 = search down 14 6 sm r/w 0 1 = search mode 0 = preset mode 13 to 00 5 to 0 and 7 to 0 fr[13:0] r/w - frequency set bits table 16. tnctrl - spi address 04 or i 2 c byte 4r + byte 5r/byte 3w + byte 4w bit description bit symbol access reset value description spi i 2 c 15 and 14 7 and 6 pupd[1:0] r/w 0 power-up power-down 00 = fm and rds off 01 = fm on and rds off 10 = not used 11 = fm and rds on 13 5 blim r/w 0 1 = japan fm band 76 mhz to 90 mhz 0 = us/europe fm band 87.5 mhz to 108 mhz 12 4 swpm r/w 0 1 = software port output is bit frrflag 0 = software port output is bit swp
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 38 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 11 3 ifctc r/w 1 1 = if count time 15.625 ms 0 = if count time 2.02 ms 10 2 afm r/w 0 1 = l-audio and r-audio muted 0 = audio not muted 09 1 smute r/w 0 1 = soft mute on 0 = off 08 0 snc r/w 0 1 = stereo noise cancellation on 0 = off 07 7 mu r/w 1 1 = l-audio and r-audio muted 0 = no hard mute 06 and 05 6 and 5 ssl[1:0] r/w 1 search stop level 00 = fm and rds off 01 = fm on and rds off 10 = not used 11 = fm and rds on 04 4 hlsi r/w 1 1 = high-side injection 0 = low-side injection 03 3 mst r/w 0 1 = forced mono 0 = stereo on 02 2 swp r/w 0 1 = swport high 0 = swport low 01 1 dtc r/w 1 1 = de-emphasis time constant 50 m s 0 = de-emphasis time constant 75 m s 00 0 ahlsi r/w 0 1 = tuner will stop during search on failed if count and correct level 0 = tuner will search continuously table 16. tnctrl - spi address 04 or i 2 c byte 4r + byte 5r/byte 3w + byte 4w bit description continued bit symbol access reset value description spi i 2 c table 17. frqchk - spi address 05 or i 2 c byte 6r + byte 7r bit symbol access reset value description spi i 2 c 15 and 14 7 and 6 - - - not used 13 to 00 5 to 0 and 7 to 0 pll[13:0] r - frequency found table 18. tunchk - spi address 06 or i 2 c byte 8r + byte 9r bit symbol access reset value description spi i 2 c 15 to 09 7 to 1 if[6:0] r - if count 08 0 tunto r - 1 = pll tuning time-out 0 = pll has settled 07 to 04 7 to 4 lev[3:0] r - level count
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 39 of 59 nxp semiconductors tea5766uk stereo fm radio + rds [1] this does not switch the radio to mono or stereo. this depends on the rf input level as shown under mono stereo blend or mono stereo switched. 03 3 ld r - 1 = pll locked is detected 0 = pll is not locked 02 2 stereo [1] r - 1 = pilot detected 0 = no pilot 01 and 00 1 and 0 - - - not used table 18. tunchk - spi address 06 or i 2 c byte 8r + byte 9r continued bit symbol access reset value description spi i 2 c table 19. testreg - spi address 07 or i 2 c byte 10r + byte 11r/byte 5w + byte 6w bit symbol access reset value description spi i 2 c 15 7 lhm r/w 0 1 = left audio output is hard muted and the radio is forced to mono 0 = not muted 14 6 rhm r/w 0 1 = right audio output is hard muted and the radio is forced to mono 0 = not muted 13 5 afmdis r/w 0 afm disable bit. when afm = 1 and tm = 1 during the tuning algorithm, afm is disabled 12 4 lhsw r/w 0 see t ab le 20 1 = level hysteresis is large 0 = level hysteresis is small 11 3 mmbs r/w 0 1 = mmbs mode on 0 = mmbs mode off 10 2 tun r/w 0 tuning programming error indicator when tm = 1 09 1 rfagc r/w 0 1 = rfagc off 0 = rfagc on 08 0 intctrl r/w 0 when tm = 1, intx follows bit intctrl; when tm = 0, then intctrl = 1 generates an interrupt on intx 07 and 06 7 and 6 - - - not used 05 5 snclev r/w 0 snclev switches the starting point mono/stereo blending 04 4 tm r/w 0 1 = software test mode and software port outputs according to t ab le 21 0 = normal operation 03 to 00 3 to 0 tb[3:0] r/w 0 test bits; t ab le 21 describes selection of signals available at pins swport and intx
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 40 of 59 nxp semiconductors tea5766uk stereo fm radio + rds table 20. lh - rssi level hysteresis rssi adc search stop level rssi hysteresis threshold level lhsw = 0 lhsw = 1 3 (snr = 40 dba) 0 (snr = 0 dba) 0 (snr = 0 dba) 5 (snr = 46 dba) 2 (snr = 37 dba) 1 (snr = 34 dba) 7 (snr = 52 dba) 4 (snr = 49 dba) 3 (snr = 40 dba) 10 (maximum snr and maximum channel separation) 7 (snr = 52 dba) 5 (snr = 46 dba) table 21. test bits test conditions: t amb =25 c, d f = 75 khz including 9 % pilot, r = l, f mod = 1 khz, de-emphasis = 50 m s, mst = 0, snc = 1, iec ?lter (200 hz to 15 khz), a-weighting ?lter. tb3 tb2 tb1 tb0 output signal pin bit tm 0000 bit swp of byte 4w, depending on bits swpm and swp or frrflag swport 0 or 1 0001 oscillator output 32.768 khz swport 1 0010lock detect bit ld swport 1 0011 pilot detected signal swport 1 0100 programmable divider swport 1 0101 intx output equal to intctrl; pin swport = low intx 1 01103.8 mhz clock swport 1 table 22. rdsr1 - spi address 08 or i 2 c byte 12r + byte 13r bit symbol access reset value description spi i 2 c 15 7 - - - not used 14 to 12 6 to 4 blid[2:0] r - block id of last block 000=a 001=b 010=c 011=d 100=c 101=e 110 = invalid block e (rbds) 111 = invalid block 11 and 10 3 and 2 - - - not used 09 and 08 1 and 0 elb[1:0] r - number of errors for last processed block 00 = no errors 01 = maximum 2 bits 10 = maximum 5 bits 11 = uncorrectable
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 41 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 07 to 05 7 to 5 bpid[2:0] r - block id of previous block 000=a 001=b 010=c 011=d 100=c 101=e 110 = invalid block e (rbds) 111 = invalid block 04 and 03 4 and 3 epb[1:0] r - number of errors for previous processed block 00 = no errors 01 = maximum 2 bits 10 = maximum 5 bits 11 = uncorrectable 02 2 sync r - 1 = rds bitstream is synchronized 0 = not synchronized 01 1 rstd r - 1 = power-on reset detected 00 0 dovf r - 1 = data over?ow occurred during read operation 0 = normal operation table 22. rdsr1 - spi address 08 or i 2 c byte 12r + byte 13r continued bit symbol access reset value description spi i 2 c table 23. rdsr2 - spi address 09 or i 2 c byte 13r + byte 15r bit symbol access reset value description spi i 2 c 15 to 00 7 to 0 and 7 to 0 bl[15:0] r - last rds data byte table 24. rdsr3 - spi address 10 or i 2 c byte 16r + byte 17r bit symbol access reset value description spi i 2 c 15 to 00 7 to 0 and 7 to 0 bp[15:0] r - previous rds data byte table 25. rdsr4 - spi address 11 or i 2 c byte 18r + byte 19r bit symbol access reset value description spi i 2 c 15 to 10 7 to 2 bbc[5:0] r - bad block count 09 to 04 1 to 0 and 7 to 4 gbc[5:0] r - good block count 03 to 00 3 to 0 - - - not used
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 42 of 59 nxp semiconductors tea5766uk stereo fm radio + rds table 26. rdsw1 - spi address 12 or i 2 c byte 20r + byte 21r/byte 7w + byte 8w bit symbol access reset value description spi i 2 c 15 7 nwsy r/w 0 1 = start new synchronization 0 = normal processing 14 and 13 6 and 5 sym[1:0] r/w 0 error correction 00 = no correction 01 = maximum 2 bits 10 = maximum 5 bits 11 = no correction 12 4 rbds r/w 0 1 = rbds processing mode 0 = rds processing mode 11 and 10 3 and 2 dac[1:0] r/w 0 rds data output mode 00=dav-a 01=dav-b 10=dav-c 11 = not used 09 to 05 1 and 0; 7to5 - - - not used 04 to 00 4 to 0 bbg[4:0] r/w 1 0000 bad blocks gain table 27. rdsw2 - spi address 13 or i 2 c byte 22r + byte 23r/byte 9w + byte 10w bit symbol access reset value description spi i 2 c 15 to 12 7 to 4 - - - not used 11 to 06 3 to 0; 7 and 6 gbl[5:0] r/w 0 these bits set the maximum number of good blocks 05 to 00 5 to 0 bbl[5:0] r/w 0 these bits set the maximum number of bad blocks table 28. manid - spi address 00 or i 2 c byte 24r + byte 25r bit symbol access reset value description spi i 2 c 15 to 12 7 to 4 version[3:0] r - version code = 0001h 11 to 01 3 to 0; 7to2 manid[10:0] r - manufacturer id code = 015h 00 0 idav r 1 1 = manufacturer id available in i 2 c-bus mode 0 = chip has no id table 29. chipid - spi address 01 or i 2 c byte 26r + byte 27r bit symbol access reset value description spi i 2 c 15 to 00 7 to 0; 7to0 chipid[15:0] r - chip identi?cation code = 5766h
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 43 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 12. limiting values [1] machine model (l = 0.75 mh, r = 10 w , c = 200 pf). [2] human body model (r = 1.5 k w , c = 100 pf). [3] charged device model; see jedec standard jesd22-c101c . 13. characteristics 13.1 general characteristics table 30. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v lo1 voltage on pin lo1 - 0.6 +4.5 v v lo2 voltage on pin lo2 - 0.6 +4.5 v v ccd digital supply voltage - 0.6 +4.5 v v cca analog supply voltage - 0.6 +4.5 v v i input voltage with respect to ground - 0.6 +4.5 v v o output voltage with respect to ground - 0.6 +4.5 v t stg storage temperature - 40 +125 c t amb ambient temperature tea5766uk functional, speci?cation not guaranteed - 30 +85 c v esd electrostatic discharge voltage machine model [1] - 200 +200 v human body model [2] pin swport - 2000 +500 v any other pin - 2000 +2000 v charged device model [3] - 500 +500 v table 31. general characteristics under all conditions a reference clock of 32.768 khz is present. symbol parameter conditions min typ max unit v cca analog supply voltage 2.6 2.7 3.6 v v cc(vco) vco supply voltage 2.6 2.7 3.6 v i cca analog supply current operating [1] - 13.5 17 ma standby mode [1] --5 m a v ccd digital supply voltage 2.6 2.7 3.6 v i ccd digital supply current operating; rds off - 350 450 m a operating; rds on - 0.75 1.5 ma standby mode - 5 10 m a sleep mode; only in i 2 c-bus; busen = high -1625 m a v vrefdig voltage on pin vrefdig v vrefdig v ccd 1.65 1.8 v ccd v
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 44 of 59 nxp semiconductors tea5766uk stereo fm radio + rds [1] includes both analog supply current on pin v cca and vco supply current on pin v cc(vco) . 13.2 reference clock the electrical characteristics as stated in section 13.4 are valid under restriction of the reference clock as speci?ed in t ab le 32 . 13.3 audio measurement ?lter the iec ?lter referenced to in the electrical characteristics of section 13.4 is de?ned in iec 60315-4. the audio bandwidth of this ?lter lies between 200 hz and 15 khz. 13.4 characteristics i vrefdig current on pin vrefdig 0 0.5 1 m a standby mode 0 0.5 1 m a f i(fm) fm input frequency 76 - 108 mhz t amb ambient temperature device meets all speci?cations - 20 - +85 c table 31. general characteristics continued under all conditions a reference clock of 32.768 khz is present. symbol parameter conditions min typ max unit table 32. reference clock de?nition, pin freqin reference clock 32.768 khz symbol parameter conditions min typ max unit f frequency t amb =25 c - 32.768 - khz d f/f relative frequency difference t amb =25 c - 20 10 -6 - +20 10 -6 t amb = - 20 c to +85 c - 150 10 -6 - +150 10 -6 d duty cycle square wave 30 - 70 % t r rise time 5 - 50 ns t f fall time 5 - 50 ns v ih high-level input voltage square wave 1.1 - v ccd v v il low-level input voltage square wave 0 - 0.7 v f jit frequency jitter integrated over 200 hz to 15000 hz --1hz table 33. characteristics all ac values are given in rms unless otherwise speci?ed. the min and max values include spread due to: v cc = 2.6 v to 3.6 v; t amb = - 20 c to +85 c, reference frequency offset + deviation and process spread. symbol parameter conditions min typ max unit antenna input including matching circuit z i input impedance f rf = 76 mhz to 108 mhz - 50 - w | s 11 | 2 input return loss f rf = 76 mhz to 108 mhz - 5-- db voltage controlled oscillator f vco vco frequency 150 - 217 mhz reference frequency input, pin freqin v freqin voltage on pin freqin switching level 0.7 0.925 1.1 v r i input resistance 1 - - m w
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 45 of 59 nxp semiconductors tea5766uk stereo fm radio + rds c i input capacitance - - 7 pf synthesizer t s settling time single frequency jump in any direction to a frequency within the frequency band (87.5 mhz to 108 mhz or 76 mhz to 90 mhz); settling limit is 5 khz of target frequency - - 50 ms d prog programmable divider frqset[15:8] = xx01 1111; frqset[7:0] = 1111 1111 - - 8191 frqset[15:8] = xx00 1000; frqset[7:0] = 0000 0000 2048 - - d prog(step) programmable divider step -1- f step step frequency - 100 - khz if counter n ifc if counter length - 7 - bit v sens sensitivity voltage - - 3 [1] m v n ifc(result) if counter result for search stop; stop level voltage < v rf <2 v [1] 31h - 3ch 49 - 60 t period 16 ms; ifctc = 1 - 15625 - m s 2 ms; ifctc = 0 - 1953 - m s n ifc(res) if counter resolution - 4096 - hz logic pins: busen, clock, data and busmode r i input resistance 2.5 - - m w v ih high-level input voltage 0.7 v vrefdig -v vrefdig + 0.3 v v il low-level input voltage - 0.3 - 0.3 v vrefdig v logic pin: data output spi mode v ol low-level output voltage i load = 2 ma 0 - 0.22 v vrefdig m w v oh high-level output voltage i load = 2 ma 0.8 v vrefdig -v vrefdig v t r(o) output rise time c l < 10 pf 5 - 20 ns t f(o) output fall time c l < 10 pf 5 - 20 ns software programmable port pin: swport v o(max) maximum output voltage i load = 150 m av vrefdig - 0.25 -v vrefdig v v o(min) minimum output voltage i load = 150 m a 0 0.2 0.45 v i sink sink current v swport = 1.8 v 0.75 1.8 5 ma i source source current v swport = 0 v 0.75 1.8 5 ma table 33. characteristics continued all ac values are given in rms unless otherwise speci?ed. the min and max values include spread due to: v cc = 2.6 v to 3.6 v; t amb = - 20 c to +85 c, reference frequency offset + deviation and process spread. symbol parameter conditions min typ max unit
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 46 of 59 nxp semiconductors tea5766uk stereo fm radio + rds pin intx v o(max) maximum output voltage v vrefdig 3 1.65 v; pull-up resistor of second device connected to intx is 18 k w 20 % v vrefdig - 0.2 -v vrefdig + 0.2 v v o(min) minimum output voltage 0 - 0.22 v vrefdig v i source source current including r pu(int) 700 900 1100 m a r pu(int) internal pull-up resistance 14.4 18 24 k w t p pulse duration 9 - 10 ms fm rf input v sens sensitivity voltage f rf = 76 mhz to 108 mhz; d f = 22.5 khz; f mod = 1 khz; (s+n/n) = 26 db; de-emphasis = 50 m s; l = r; iec ?lter + a-weighting ?lter -2 [1] 3 [1] m v s/n signal-to-noise ratio f rf = 76 mhz to 108 mhz; d f = 22.5 khz; f mod = 1 khz; de-emphasis = 50 m s; l = r; v rf =10 m v [1] ; iec ?lter + a-weighting ?lter 45 - - dba ip3 ib in-band third-order intercept point d f 1 = 200 khz; d f 2 = 400 khz; f tune = 76 mhz to 108 mhz 82 95 - db m v ip3 ob out-band third-order intercept point d f 1 = 4 mhz; d f 2 = 8 mhz; f tune = 76 mhz to 108 mhz 88 100 - db m v if ?lter f c center frequency 217 221 233 khz s 200 200 khz selectivity d f= 200 khz; f rf = 76 mhz to 108 mhz; measured according to en 55020; de-emphasis 50 m s 16 - - db s fm fm selectivity d f = 300 khz minimum; f rf = 76 mhz to 108 mhz; except image frequency band; measured according to en 55020; de-emphasis 50 m s 35 - - db a f(image) image frequency rejection d f = 450 khz; measured according to en 55020; image rejection de?ned as difference between image and co-channel response; de-emphasis 50 m s 25 - - db fm if level detector and mute voltage, see figure 20 d g gain deviation deviation from average curve - 2 - +2 db v adc(start) start adc voltage extrapolated 0.75 [1] 1.6 [1] 2.5 [1] m v g adc(step) step of adc gain average 2.5 2.8 3 db soft mute v mute(start) start mute voltage smute = 1 2 3.5 5 m v table 33. characteristics continued all ac values are given in rms unless otherwise speci?ed. the min and max values include spread due to: v cc = 2.6 v to 3.6 v; t amb = - 20 c to +85 c, reference frequency offset + deviation and process spread. symbol parameter conditions min typ max unit
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 47 of 59 nxp semiconductors tea5766uk stereo fm radio + rds a mute mute attenuation v rf = 1.26 m v [1] ; l=r; d f = 22.5 khz; f mod = 1 khz; de-emphasis = 75 m s; iec ?lter; smute = 1 5 5.8 8 db stereo decoder, pins vafl and vafr v o output voltage v rf = 2 mv [1] ; l=r; d f = 22.5 khz; f mod = 1 khz; de-emphasis = 75 m s 60 75 90 mv r o output resistance mu = lhm = rhm = 0; afm = 0 or afm = 1 250 350 400 w hard mute; mu = lhm = rhm = 1; afm = 0 or afm = 1 500 - - k w standby mode; pupd0 = 0 1 - - m w i o output current minimum load resistance = 10 k w 80 100 120 m a | g v | voltage gain difference v rf = 2 mv [1] ; l=r; d f = 75 khz; f mod = 1 khz; iec ?lter; de-emphasis = 75 m s - 0.5 - +0.5 db a cs(stereo) stereo channel separation v rf = 2 mv [1] ; d f = 75 khz including 9 % pilot; r= 0 and l= 1 or r= 1 and l= 0; f mod = 1 khz; iec ?lter; mst = 0; snc = 0 or snc = 1 + snclev = 1 27 45 - db f - 3db(l) low frequency - 3db point v rf = 2 mv [1] ; d f = 22.5 khz; l = r; pre-emphasis = 75 m s; de-emphasis = 75 m s - - 20 hz f - 3db(h) high frequency - 3 db point v rf = 2 mv [1] ; d f = 22.5 khz; l = r; pre-emphasis = 75 m s; de-emphasis = 75 m s 15 - - khz (s+n)/n signal plus noise-to-noise ratio v rf = 2 mv [1] ; l=r; d f = 22.5 khz; f mod = 1 khz; de-emphasis = 50 m s; iec ?lter + a-weighting ?lter mono 53 57 - dba stereo; d f pilot = 6.75 khz 49 53 - dba a resp(sp) spurious response relative to d f = 22.5 khz; f mod = 1 khz (mono); v rf =2mv [1] ; de-emphasis = 50 m s; iec ?lter + a-weighting ?lter -- - 60 db table 33. characteristics continued all ac values are given in rms unless otherwise speci?ed. the min and max values include spread due to: v cc = 2.6 v to 3.6 v; t amb = - 20 c to +85 c, reference frequency offset + deviation and process spread. symbol parameter conditions min typ max unit
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 48 of 59 nxp semiconductors tea5766uk stereo fm radio + rds thd total harmonic distortion mono; v rf = 2 mv [1] ; l=r; de-emphasis = 75 m s d f = 75 khz; f mod = 400 hz - 0.4 0.8 % d f = 75 khz; f mod = 1 khz - 0.4 0.8 % d f = 75 khz; f mod = 3 khz - 0.4 0.8 % d f = 100 khz; f mod = 1 khz - 0.5 1 % stereo; v rf =2mv [1] ; d f = 75 khz; l = r including 9 % pilot; de-emphasis = 75 m s f mod = 1 khz - 0.5 1.5 % f mod = 3 khz - 0.5 1.5 % a am am suppression l = r; d f = 22.5 khz; f mod = 1 khz; m = 0.3; de-emphasis = 75 m s; iec ?lter; a-weighting ?lter v rf =20 m v [1] 40 - - db v rf = 200 m vto20mv [1] 45 - - db a pilot pilot suppression related to d f = 75 khz; including 9 % pilot; l = 0 and r = 1 or l = 1 and r = 0; f mod = 1 khz; de-emphasis = 75 m s 40 50 - db d f pilot pilot frequency deviation stereo; required for pilot detection; v rf = 2 mv [1] 1.8 3.6 5.8 khz a hys(pilot) pilot hysteresis v rf = 2 mv [1] 2 2.5 4 db t deemp de-emphasis time constant dtc = 1 (50 m s) 40 50 60 m s dtc = 0 (75 m s) 60 75 90 m s mono stereo blend v start(blend) blend start voltage stereo channel separation = 1 db; snc = 1 snclev = 0 8 [1] 12 [1] 20 [1] m v snclev =1 4 [1] 6 [1] 10 [1] m v a cs(stereo) stereo channel separation v rf = 70 m v [1] ; d f = 75 khz; r = 0 and l = 1 or r = 1 and l = 0; including 9 % pilot; f mod = 1 khz; mst = 0; snc = 1; snclev = 0 81218db mono stereo switched v sw switch voltage d f = 75 khz; including 9 % pilot; f mod = 1 khz; snc = 0; spread due to rssi variation 65 [1] 90 [1] 115 [1] m v |d v sw /v sw | switch voltage deviation over switch voltage ratio d f = 75 khz; including 9 % pilot; f mod = 1 khz; snc = 0 234db table 33. characteristics continued all ac values are given in rms unless otherwise speci?ed. the min and max values include spread due to: v cc = 2.6 v to 3.6 v; t amb = - 20 c to +85 c, reference frequency offset + deviation and process spread. symbol parameter conditions min typ max unit
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 49 of 59 nxp semiconductors tea5766uk stereo fm radio + rds [1] emf value. mute functions a mute mute attenuation d f = 75 khz; mono; iec ?lter afm = 1 or rhm = 1; lhm = 0 - - - 60 db afm = 1 or lhm = 1; rhm = 0 - - - 60 db mu = 1 - - - 80 db rds ?lter/demodulator/decoder v sens sensitivity voltage f rf = 87.5 mhz to 108 mhz; d f = 22.5 khz; f af = 1 khz; l = r; d f rds = 2 khz; block quality rate 3 95 %; sym1 = 0 and sym0 = 0; average over 2000 blocks -14 [1] 20 [1] m v f c center frequency 56 57 58 khz b bandwidth 2.5 3 3.5 khz table 33. characteristics continued all ac values are given in rms unless otherwise speci?ed. the min and max values include spread due to: v cc = 2.6 v to 3.6 v; t amb = - 20 c to +85 c, reference frequency offset + deviation and process spread. symbol parameter conditions min typ max unit v adc(start) is the starting point of the curve. taking the starting point the curve shows a monotone increase, increasing with the average step size g adc(step) . the maximum deviation from the average curve is d g. fig 20. fm if level detector and mute voltage 001aaf263 v sens ( m v) 1 10 3 10 2 10 5 10 15 adc level 0 g v start(adc) d g
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 50 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 14. application information fig 21. application diagram 001aaf453 2 if filter n1 i/q mixer 1st fm rf agc lna power supply auto align reference buffer soft mute sds i 2 c-bus interface mpx decoder tuning system mono pilot prog. div out ref. div out mux sw port vco gndd d6 e6 e5 e4 tmute vafr vafl mpxout iss busen intx limiter level adc demodulator 57 khz bp register rds/rbds decoder interface register if counter tea5766uk gnda b5 c1 b6 c6 c5 freqin a6 v cca rfin1 fm antenna rfin2 gnd(rf) a2 100 pf 27 pf l1 120 nh 47 pf a1 a3 a4 a5 b1 c2 vrefdig e3 clock e2 data e1 d2, d3 d5 b2 v ccd d1 swport loopsw 10 nf 100 nf 100 nf 10 k w 100 k w cpout v cc(vco) v cc(vco) lo1 47 nh l2 lo2
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 51 of 59 nxp semiconductors tea5766uk stereo fm radio + rds table 34. list of components symbol parameter type l1 120 nh murata lqw15anr12j00 or equivalent, qmin = 20 (f = 100 mhz), tolerance 5% l2 47 nh murata lqw15an47nj00 or equivalent, qmin = 25 (f = 250 mhz), tolerance 5% r10k w and 100 k w tolerance 10 % maximum c 27 pf, 47 pf, 100 pf, 10 nf and 100 nf tolerance 10 % maximum
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 52 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 15. package outline fig 22. package outline tea5766 (wlcsp25) references outline version european projection issue date iec jedec jeita tea5766 tea5766 06-02-23 06-03-03 unit a max mm 0.64 0.26 0.22 0.38 0.34 0.34 0.30 3.35 3.30 3.30 3.25 a 1 dimensions (mm are the original dimensions) wlcsp25: wafer level chip-size package; 25 bumps; 3.3 x 3.25 x 0.6 mm bump a1 index area a 2 b d e e 2 2 e 1 2.5 e 4 0.15 e 3 0.2 e 0.5 v 0.01 w 0.04 y 0.02 0 1 2 3 mm scale e 3 e 2 e b e 4 e 1 e a c b ? v m c ? w m a b c d e 246 135 b a d e detail x a a 2 a 1 c y x
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 53 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 16. soldering 16.1 introduction to soldering wlcsp packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering wlcsp (wafer level chip-size packages) can be found in application note an10439 wafer level chip scale package and in application note an10365 surface mount re?ow soldering description . wave soldering is not suitable for this package. 16.2 board mounting board mounting of a wlcsp requires several steps: 1. solder paste printing on the pcb 2. component placement with a pick and place machine 3. the re?ow soldering itself 16.3 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 23 ) than a pbsn process, thus reducing the process window ? solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature), and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 35 and 36 table 35. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 36. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 54 of 59 nxp semiconductors tea5766uk stereo fm radio + rds moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 23 . for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 16.3.1 stand off the stand off between the substrate and the chip is determined by: ? the amount of printed solder on the substrate ? the size of the solder land on the substrate ? the bump height on the chip the higher the stand off, the better the stresses are released due to tec (thermal expansion coef?cient) differences between substrate and chip. 16.3.2 quality of solder joint a ?ip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. the surface of the joint should be smooth and the shape symmetrical. the soldered joints on a chip should be uniform. voids in the bumps after re?ow can occur during the re?ow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. no failures have been found to be related to these voids. solder joint inspection after re?ow can be done with x-ray to monitor defects such as bridging, open circuits and voids. msl: moisture sensitivity level fig 23. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 55 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 16.3.3 rework in general, rework is not recommended. by rework we mean the process of removing the chip from the substrate and replacing it with a new chip. if a chip is removed from the substrate, most solder balls of the chip will be damaged. in that case it is recommended not to re-use the chip again. device removal can be done when the substrate is heated until it is certain that all solder joints are molten. the chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. the surface of the substrate should be carefully cleaned and all solder and ?ux residues and/or under?ll removed. when a new chip is placed on the substrate, use the ?ux process instead of solder on the solder lands. apply ?ux on the bumps at the chip side as well as on the solder pads on the substrate. place and align the new chip while viewing with a microscope. to re?ow the solder, use the solder pro?le shown in application note an10365 surface mount re?ow soldering description . 16.3.4 cleaning cleaning can be done after re?ow soldering. 17. references [1] the i 2 c-bus speci?cation version 2.1, january 2000. [2] bs en 62106 speci?cation of the radio data system (rds) for vhf/fm sound broadcasting in the frequency range from 87.5 to 108 mhz, 2001. [3] data sheet tef6892h car radio integrated signal processor, 2003 oct 21. [4] jesd22-c101c jedec standard for charged-device model esd test method. [5] data sheet saa6588 rds/rbds pre-processor, 2002 jan 14. [6] en 55020 sound and television broadcast receivers and associated equipment-immunity characteristics- limits and methods of measurement, may 2002. [7] rds: the radio data system dietmar kopitz and bev marks.
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 56 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 18. revision history table 37. revision history document id release date data sheet status change notice supersedes tea5766uk_1 20070322 product data sheet - -
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 57 of 59 nxp semiconductors tea5766uk stereo fm radio + rds 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 19.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 19.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 20. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
tea5766uk_1 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 01 22 march 2007 58 of 59 continued >> nxp semiconductors tea5766uk stereo fm radio + rds 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 low noise rf ampli?er . . . . . . . . . . . . . . . . . . . 5 7.2 fm mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.3 vco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.4 reference frequency . . . . . . . . . . . . . . . . . . . . 5 7.5 tuning system. . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.6 band limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.7 rf agc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.8 if ?lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.9 fm demodulator . . . . . . . . . . . . . . . . . . . . . . . . 7 7.10 if counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.10.1 if counter correct channel checking. . . . . . . . . 7 7.10.2 if counter count time . . . . . . . . . . . . . . . . . . . . 7 7.11 level voltage generator and level analog-to-digital converter . . . . . . . . . . . . . . . . 7 7.12 mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.12.1 soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.12.2 hard mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.12.3 audio frequency mute (afm). . . . . . . . . . . . . . 8 7.12.4 speci?cation of mute modes. . . . . . . . . . . . . . . 8 7.13 mpx decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.14 signal depending mono/stereo blend (stereo noise cancellation) . . . . . . . . . . . . . . . . . . . . . . 8 7.15 software programmable port . . . . . . . . . . . . . . 8 7.16 standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.17 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.18 rds/rbds demodulator . . . . . . . . . . . . . . . . . 9 7.19 rds/rbds decoder . . . . . . . . . . . . . . . . . . . . 10 7.20 auto search and preset mode. . . . . . . . . . . . . 10 7.20.1 auto high-side and low-side injection stop switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.20.2 muting during search or preset . . . . . . . . . . . . 11 7.21 rds update or alternative frequency jump. . . 12 7.21.1 muting during rds update . . . . . . . . . . . . . . . 13 8 interrupt handling . . . . . . . . . . . . . . . . . . . . . . 14 8.1 interrupt register . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 interrupt clearing. . . . . . . . . . . . . . . . . . . . . . . 15 8.1.2 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 interrupt ?ags and behavior . . . . . . . . . . . . . . 18 8.2.1 multiple interrupt events . . . . . . . . . . . . . . . . . 18 8.2.2 data available: davflg. . . . . . . . . . . . . . . . . 18 8.2.3 rds synchronization: lsyncfl . . . . . . . . . . 18 8.2.4 if frequency: ifflag. . . . . . . . . . . . . . . . . . . 19 8.2.5 rssi threshold: levflag . . . . . . . . . . . . . . . 19 8.2.6 frequency ready: frrflag . . . . . . . . . . . . . 20 8.2.7 band limit: blflag . . . . . . . . . . . . . . . . . . . . 20 8.3 interrupt line: pin intx . . . . . . . . . . . . . . . . . . 20 9 rds data processing . . . . . . . . . . . . . . . . . . . 21 9.1 dav-a processing mode. . . . . . . . . . . . . . . . . 21 9.2 dav-b processing mode and fast pi search mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3 dav-c reduced processing mode . . . . . . . . . 25 9.4 synchronization . . . . . . . . . . . . . . . . . . . . . . . 27 9.4.1 conditions for synchronization . . . . . . . . . . . . 27 9.4.2 modi?ed mobile broadcast service (mmbs) mode . . . . . . . . . . . . . . . . . . . . . . . . 28 9.4.3 data over?ow . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.5 rds ?ag behavior during read action . . . . . . 28 9.6 error detection and reporting . . . . . . . . . . . . . 30 9.7 rds data - reading from registers . . . . . . . . . 30 10 control interface. . . . . . . . . . . . . . . . . . . . . . . 30 10.1 selection between i 2 c-bus and spi-bus . . . . 30 10.2 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.1 data transfer to the tea5766uk . . . . . . . . . . 31 10.2.2 i 2 c-bus output driving characteristics. . . . . . . 32 10.2.3 i 2 c-bus timing diagram. . . . . . . . . . . . . . . . . . 33 10.3 spi-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.2 register description . . . . . . . . . . . . . . . . . . . . 36 12 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 43 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43 13.1 general characteristics . . . . . . . . . . . . . . . . . 43 13.2 reference clock . . . . . . . . . . . . . . . . . . . . . . . 44 13.3 audio measurement ?lter . . . . . . . . . . . . . . . . 44 13.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 14 application information . . . . . . . . . . . . . . . . . 50 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 52 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.1 introduction to soldering wlcsp packages. . 53 16.2 board mounting . . . . . . . . . . . . . . . . . . . . . . . 53 16.3 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 53 16.3.1 stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
nxp semiconductors tea5766uk stereo fm radio + rds ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 22 march 2007 document identifier: tea5766uk_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 16.3.2 quality of solder joint . . . . . . . . . . . . . . . . . . . 54 16.3.3 rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16.3.4 cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . 56 19 legal information. . . . . . . . . . . . . . . . . . . . . . . 57 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 57 19.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 20 contact information. . . . . . . . . . . . . . . . . . . . . 57 21 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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